The following issues were found
drivers/clk/rockchip/clk-rk3288.c
1 issues
Line: 182
};
static const struct rockchip_cpuclk_reg_data rk3288_cpuclk_data = {
.core_reg[0] = RK3288_CLKSEL_CON(0),
.div_core_shift[0] = 8,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
Reported by Cppcheck.
drivers/clk/rockchip/clk-rk3308.c
1 issues
Line: 112
};
static const struct rockchip_cpuclk_reg_data rk3308_cpuclk_data = {
.core_reg[0] = RK3308_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0xf,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
Reported by Cppcheck.
drivers/clk/rockchip/clk-rk3328.c
1 issues
Line: 133
};
static const struct rockchip_cpuclk_reg_data rk3328_cpuclk_data = {
.core_reg[0] = RK3328_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 3,
Reported by Cppcheck.
drivers/clk/rockchip/clk-rk3368.c
1 issues
Line: 157
#define IFLAGS ROCKCHIP_INVERTER_HIWORD_MASK
static const struct rockchip_cpuclk_reg_data rk3368_cpuclkb_data = {
.core_reg[0] = RK3368_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
Reported by Cppcheck.
drivers/clk/rockchip/clk-rk3399.c
1 issues
Line: 294
RK3399_PMU_CLKSEL_CON(1), 14, 1, MFLAGS);
static const struct rockchip_cpuclk_reg_data rk3399_cpuclkl_data = {
.core_reg[0] = RK3399_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 3,
.mux_core_main = 0,
Reported by Cppcheck.
drivers/clk/rockchip/clk-rk3568.c
1 issues
Line: 186
};
static const struct rockchip_cpuclk_reg_data rk3568_cpuclk_data = {
.core_reg[0] = RK3568_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.core_reg[1] = RK3568_CLKSEL_CON(0),
.div_core_shift[1] = 8,
.div_core_mask[1] = 0x1f,
Reported by Cppcheck.
drivers/clk/rockchip/clk-rv1108.c
1 issues
Line: 109
};
static const struct rockchip_cpuclk_reg_data rv1108_cpuclk_data = {
.core_reg[0] = RV1108_CLKSEL_CON(0),
.div_core_shift[0] = 0,
.div_core_mask[0] = 0x1f,
.num_cores = 1,
.mux_core_alt = 1,
.mux_core_main = 0,
Reported by Cppcheck.
drivers/clk/samsung/clk-exynos-clkout.c
1 issues
Line: 105
Column: 8
CWE codes:
119
120
Suggestion:
Perform bounds checking, use functions that limit length, or ensure that the size is larger than the maximum possible length
static int exynos_clkout_probe(struct platform_device *pdev)
{
const char *parent_names[EXYNOS_CLKOUT_PARENTS];
struct clk *parents[EXYNOS_CLKOUT_PARENTS];
struct exynos_clkout *clkout;
int parent_count, ret, i;
u32 mux_mask;
Reported by FlawFinder.
drivers/clk/sifive/sifive-prci.c
1 issues
Line: 158
Column: 2
CWE codes:
120
Suggestion:
Make sure destination can always hold the source data
{
__prci_writel(__prci_wrpll_pack(c), pwd->cfg0_offs, pd);
memcpy(&pwd->c, c, sizeof(*c));
}
/**
* __prci_wrpll_write_cfg1() - write Clock enable/disable configuration
* into the PRCI
Reported by FlawFinder.
drivers/clk/socfpga/clk-gate-a10.c
1 issues
Line: 104
Column: 8
CWE codes:
119
120
Suggestion:
Perform bounds checking, use functions that limit length, or ensure that the size is larger than the maximum possible length
struct clk_hw *hw_clk;
struct socfpga_gate_clk *socfpga_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
if (WARN_ON(!socfpga_clk))
Reported by FlawFinder.