The following issues were found
drivers/clk/socfpga/clk-gate.c
1 issues
Line: 180
Column: 8
CWE codes:
119
120
Suggestion:
Perform bounds checking, use functions that limit length, or ensure that the size is larger than the maximum possible length
struct clk_hw *hw_clk;
struct socfpga_gate_clk *socfpga_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct clk_ops *ops;
int rc;
int err;
Reported by FlawFinder.
drivers/clk/socfpga/clk-periph-a10.c
1 issues
Line: 67
Column: 8
CWE codes:
119
120
Suggestion:
Perform bounds checking, use functions that limit length, or ensure that the size is larger than the maximum possible length
struct clk_hw *hw_clk;
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
u32 fixed_div;
u32 div_reg[3];
Reported by FlawFinder.
drivers/clk/socfpga/clk-periph.c
1 issues
Line: 57
Column: 8
CWE codes:
119
120
Suggestion:
Perform bounds checking, use functions that limit length, or ensure that the size is larger than the maximum possible length
struct clk_hw *hw_clk;
struct socfpga_periph_clk *periph_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
int rc;
u32 fixed_div;
u32 div_reg[3];
Reported by FlawFinder.
drivers/clk/socfpga/clk-pll-a10.c
1 issues
Line: 73
Column: 8
CWE codes:
119
120
Suggestion:
Perform bounds checking, use functions that limit length, or ensure that the size is larger than the maximum possible length
struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFGPA_MAX_PARENTS];
struct clk_init_data init;
struct device_node *clkmgr_np;
int i = 0;
of_property_read_u32(node, "reg", ®);
Reported by FlawFinder.
drivers/clk/socfpga/clk-pll.c
1 issues
Line: 80
Column: 8
CWE codes:
119
120
Suggestion:
Perform bounds checking, use functions that limit length, or ensure that the size is larger than the maximum possible length
struct clk_hw *hw_clk;
struct socfpga_pll *pll_clk;
const char *clk_name = node->name;
const char *parent_name[SOCFPGA_MAX_PARENTS];
struct clk_init_data init;
struct device_node *clkmgr_np;
int err;
of_property_read_u32(node, "reg", ®);
Reported by FlawFinder.
drivers/clk/spear/clk.h
1 issues
Line: 105
Column: 8
CWE codes:
119
120
Suggestion:
Perform bounds checking, use functions that limit length, or ensure that the size is larger than the maximum possible length
struct clk_pll {
struct clk_hw hw;
struct clk_vco *vco;
const char *parent[1];
spinlock_t *lock;
};
typedef unsigned long (*clk_calc_rate)(struct clk_hw *hw, unsigned long prate,
int index);
Reported by FlawFinder.
drivers/clk/sunxi/clk-a10-mod1.c
1 issues
Line: 26
Column: 8
CWE codes:
119
120
Suggestion:
Perform bounds checking, use functions that limit length, or ensure that the size is larger than the maximum possible length
struct clk *clk;
struct clk_mux *mux;
struct clk_gate *gate;
const char *parents[4];
const char *clk_name = node->name;
void __iomem *reg;
int i;
reg = of_io_request_and_map(node, 0, of_node_full_name(node));
Reported by FlawFinder.
drivers/clk/sunxi/clk-a20-gmac.c
1 issues
Line: 58
Column: 8
CWE codes:
119
120
Suggestion:
Perform bounds checking, use functions that limit length, or ensure that the size is larger than the maximum possible length
struct clk_mux *mux;
struct clk_gate *gate;
const char *clk_name = node->name;
const char *parents[SUN7I_A20_GMAC_PARENTS];
void __iomem *reg;
if (of_property_read_string(node, "clock-output-names", &clk_name))
return;
Reported by FlawFinder.
drivers/clk/sunxi/clk-factors.c
1 issues
Line: 188
Column: 8
CWE codes:
119
120
Suggestion:
Perform bounds checking, use functions that limit length, or ensure that the size is larger than the maximum possible length
struct clk_hw *gate_hw = NULL;
struct clk_hw *mux_hw = NULL;
const char *clk_name = node->name;
const char *parents[FACTORS_MAX_PARENTS];
int ret, i = 0;
/* if we have a mux, we will have >1 parents */
i = of_clk_parent_fill(node, parents, FACTORS_MAX_PARENTS);
Reported by FlawFinder.
drivers/clk/sunxi/clk-simple-gates.c
1 issues
Line: 70
CWE codes:
476
}
for (j = 0; j < nprotected; j++)
if (protected[j] == index)
clk_prepare_enable(clk_data->clks[index]);
}
clk_data->clk_num = number + 1;
Reported by Cppcheck.